An Optimal Implementation on FPGA of a Hopfield Neural Network-Reference-Cited by-同舟云学术

An Optimal Implementation on FPGA of a Hopfield Neural Network

Published:2011-08-22 Issue: Volume:2011 Page:1-9
ISSN:1687-7594
Container-title:Advances in Artificial Neural Systems
language:en
Short-container-title:Advances in Artificial Neural Systems

Author:

Mansour W.¹,Ayoubi R.²,Ziade H.³,Velazco R.¹,EL Falou W.³⁴

Affiliation:

1. TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble, France

2. Department of Computer Engineering, University of Balamand, Tripoli, Lebanon

3. Electrical and Electronics Department, Faculty of Engineering I, Lebanese University, El Arz Street, El Kobbe, Tripoli, Lebanon

4. Lebanese French University of Technology and Applied Sciences, Tripoli, Lebanon

Abstract

The associative Hopfield memory is a form of recurrent Artificial Neural Network (ANN) that can be used in applications such as pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper presents the implementation of the Hopfield Neural Network (HNN) parallel architecture on a SRAM-based FPGA. The main advantage of the proposed implementation is its high performance and cost effectiveness: it requires O(1) multiplications and O(log⁡ N) additions, whereas most others require O(N) multiplications and O(N) additions.

Publisher

Hindawi Limited

Link

http://downloads.hindawi.com/archive/2011/189368.pdf

Reference9 articles.

1. An FPGA implementation of a neural optimization of block truncation coding for image/video compression

2. A Hopfield Neural Classifier and Its FPGA Implementation for Identification of Symmetrically Structured DNA Motifs

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