Placement and Routing for Performance-Oriented FPGA Layout-Reference-Cited by-同舟云学术

Placement and Routing for Performance-Oriented FPGA Layout

Published:1998-01-01 Issue:1 Volume:7 Page:97-110
ISSN:1065-514X
Container-title:VLSI Design
language:en
Short-container-title:VLSI Design

Author:

Alexander Michael J.¹,Cohoon James P.²,Ganley Joseph L.³,Robins Gabriel²

Affiliation:

1. School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA 99164-2752, USA

2. Department of Computer Science, University of Virginia, Charlottesville, VA 22903-2442, USA

3. Cadence Design Systems, lnc., San Jose, CA 95134-1937, USA

Abstract

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route several benchmarks.

Funder

National Science Foundation

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture

Link

http://downloads.hindawi.com/archive/1998/038483.pdf

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