Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm

Author:

Ren Huan1,Dutt Shantanu1

Affiliation:

1. Department of ECE, University of Illinois at Chicago, Chicago, IL 60607, USA

Abstract

We propose a timing-driven discrete cell-sizing algorithm that can address total cell size and/or leakage power constraints. We model cell sizing as a “discretized” mincost network flow problem, wherein available sizes of each cell are modeled as nodes. Flow passing through a node indicates the choice of the corresponding cell size, and the total flow cost reflects the timing objective function value corresponding to these choices. Compared to other discrete optimization methods for cell sizing, our method can obtain near-optimal solutions in a time-efficient manner. We tested our algorithm on ISCAS’85 benchmarks, and compared our results to those produced by an optimal dynamic programming- (DP-) based method. The results show that compared to the optimal method, the improvements to an initial sizing solution obtained by our method is only 1% (3%) worse when using a 180 nm (90 nm) library, while being 40–60 times faster. We also obtained results for ISPD’12 cell-sizing benchmarks, under leakage power constraint, and compared them to those of a state-of-the-art approximate DP method (optimal DP runs out of memory for the smallest of these circuits). Our results show that we are only 0.9% worse than the approximate DP method, while being more than twice as fast.

Funder

National Science Foundation

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Parametric analysis of schematic for efficient sub-system design with MOSFET’s scaling factors;Materials Today: Proceedings;2021-03

2. Provably Fast and Near-Optimum Gate Sizing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-12

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