Author:
Bujjibabu P.,Babulu K.,Kamaraju M.
Reference37 articles.
1. Moore’s law: past, present and future;Schaller;IEEE Spectrum,1997
2. A fuzzy optimization approach for variation aware power minimization during gate sizing;Mahalingam;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2008
3. M. Delaurenti, G. Masera, G. Piccinini, M. R. Roch, and M. Zamboni, A cmos power-delay model for cad optimization tools, in Low-Power Design, IEEE Alessandro Volta Memorial Workshop on, 1999, pp. 72–72.
4. Simultaneous voltage scaling and gate sizing for low-power design;Chen;IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing,2002
5. Fast and near-optimal timing-driven cell sizing under cell area and leakage power constraints using a simplified discrete network flow algorithm;Ren;VLSI Design,2013