Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits

Abstract

When used in conjunction with the current floorplan and the optimization technique in circuit design engineering, this research allows for the evaluation of design parameters that can be used to reduce congestion during integrated circuit fabrication. Testing the multiple alternative consequences of IC design will be extremely beneficial in this situation, as will be demonstrated further below. If the importance of placement and routing congestion concerns is underappreciated, the IC implementation may experience significant nonlinear problems throughout the process as a result of the underappreciation of placement and routing congestion concerns. The use of standard optimization techniques in integrated circuit design is not the most effective strategy when it comes to precisely estimating nonlinear aspects in the design of integrated circuits. To this end, advanced tools such as Xilinx VIVADO and the ICC2 have been developed, in addition to the ICC1 and VIRTUOSO, to explore for computations and recover the actual parameters that are required to design optimal placement and routing for well-organized and ordered physical design. Furthermore, this work employs the perimeter degree technique (PDT) to measure routing congestion in both horizontal and vertical directions for a silicon chip region and then applies the technique to lower the density of superfluous routing (DSR) (PDT). Recently, a metaheuristic approach to computation has increased in favor, particularly in the last two decades. It is a classic graph theory problem, and it is also a common topic in the field of optimization. However, it does not provide correct information about where and how nodes should be put, despite its popularity. Consequently, in conjunction with the optimized floorplan data, the optimized model created by the Improved Harmonic Search Optimization algorithm undergoes testing and investigation in order to estimate the amount of congestion that occurs during the routing process in VLSI circuit design and to minimize the amount of congestion that occurs.