An Efficient Parallel VLSI Sorting Architecture

Author:

Zhang Yanjun1,Zheng S. Q.2

Affiliation:

1. Research Group, Sabre, Inc., 1 East Kirkwood Blvd., MD 7390, Southlake 76092, TX, USA

2. Department of Computer Science, Box 830688, MS EC31, University of Texas at Dallas, Richardson 75083-0688, TX, USA

Abstract

We present a new parallel sorting algorithm that uses a fixed-size sorter iteratively to sort inputs of arbitrary size. A parallel sorting architecture based on this algorithm is proposed. This architecture consists of three components, linear arrays that support constant-time operations, a multilevel sorting network, and a termination detection tree, all operating concurrently in systolic processing fashion. The structure of this sorting architecture is simple and regular, highly suitable for VLSI realization. Theoretical analysis and experimental data indicate that the performance of this architecture is likely to be excellent in practice.

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture

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