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VLSI architecture for Vasanth sorting to denoise image with minimum comparators

  • Published:2019-11 Issue: Volume:71 Page:102880
  • ISSN:0141-9331
  • Container-title:Microprocessors and Microsystems
  • language:en
  • Short-container-title:Microprocessors and Microsystems

Author:

Vasanth K.,Sindhu E.,Varatharajan R.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference25 articles.

1. Design and analysis of comparator using different logic style of full adder;Rajasekhar;Int. J. Eng. Res. Appl.,2014

2. Comparator design using full adder;Patel;Int. J. Res. Eng. Technol.,2014

3. 2-Bit magnitude comparator design using different logic styles;Anjuli;Int. J. Eng. Sci. Inven.,2013

4. Design of efficient reversible binary comparator;Rangaraju,2011

5. BDD based logic synthesis and optimization for low power comparator circuit;Sinha,2018

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1. 45nm Technology based 8-Bit Data Comparator Architecture for Rank ordering Image Applications;2022 International Conference on Edge Computing and Applications (ICECAA);2022-10-13

2. FPGA implementation of hybrid recursive reversable box filter-based fast adaptive bilateral filter for image denoising;Microprocessors and Microsystems;2022-04

3. Area Efficient Parallel Median Filter Using Approximate Comparator and Faithful Adder;IET Circuits, Devices & Systems;2020-11

4. Image classification based on high-dimensional feature retrieval intelligent algorithm;Microprocessors and Microsystems;2020-11

5. Double Balanced Mixer with noise reduction for RF Receiver using Cadence 180nm Technology;2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS);2020-03
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