Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

Author:

Kritikos William V.1,Schmidt Andrew G.1,Sass Ron1,Anderson Erik K.2,French Matthew2

Affiliation:

1. Reconfigurable Computing Systems Laboartory, ECE Deptartment, UNC Charlotte, 9201 University City Boulevad, Charlotte, NC 28223, USA

2. Information Sciences Institute, University of Southern California, 3811 North Fairfax Drive, Suite 200, Arlington, VA 22203, USA

Abstract

The reconfigurable data-stream hardware software architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core Systems on a programmable chip (MCSoPC). Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software and/or hardware, that communicate over a seamless interface. Redsharc incorporates two on-chip networks that directly implement the API to support high-performance systems with numerous hardware kernels. This paper documents the API, describes the common infrastructure, and quantifies the performance of a complete implementation. Furthermore, the overhead, in terms of resource utilization, is reported along with the ability to integrate hard and soft processor cores with purely hardware kernels being demonstrated.

Publisher

Hindawi Limited

Subject

Hardware and Architecture

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. ZyPy: Intercepting NumPy operations for acceleration on FPGAs;Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies;2023-06-14

2. Evaluating Rapid Application Development with Python for Heterogeneous Processor-Based FPGAs;2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2017-04

3. Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration;International Journal of Reconfigurable Computing;2012

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