An architecture and compiler for scalable on-chip communication

Author:

Jian Liang ,Laffely A.,Srinivasan S.,Tessier R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 36 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. High-level synthesis of on-chip multiprocessor architectures based on answer set programming;Journal of Parallel and Distributed Computing;2018-07

2. Review of Network on Chip Architectures;Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering);2017-07-07

3. Power Optimization Techniques for Multicore SoCs;Advanced Multicore Systems-On-Chip;2017

4. MACS: A Highly Customizable Low-Latency Communication Architecture;IEEE Transactions on Parallel and Distributed Systems;2016-01-01

5. An FPGA-Based Reconfigurable Mesh Many-Core;IEEE Transactions on Computers;2014-12-01

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