Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs

Author:

Hussain Hanaa M.1,Benkrid Khaled1,Ebrahim Ali1,Erdogan Ahmet T.1,Seker Huseyin2

Affiliation:

1. School of Engineering, University of Edinburgh, King’s Buildings, Mayfield Road, Edinburgh EH9 3JL, UK

2. Bio-Health Informatics Research Group, Centre for Computational Intelligence, De Montfort University, Leicester LE1 9BH, UK

Abstract

K-means clustering has been widely used in processing large datasets in many fields of studies. Advancement in many data collection techniques has been generating enormous amounts of data, leaving scientists with the challenging task of processing them. Using General Purpose Processors (GPPs) to process large datasets may take a long time; therefore many acceleration methods have been proposed in the literature to speed up the processing of such large datasets. In this work, a parameterized implementation of the K-means clustering algorithm in Field Programmable Gate Array (FPGA) is presented and compared with previous FPGA implementation as well as recent implementations on Graphics Processing Units (GPUs) and GPPs. The proposed FPGA has higher performance in terms of speedup over previous GPP and GPU implementations (two orders and one order of magnitude, resp.). In addition, the FPGA implementation is more energy efficient than GPP and GPU (615x and 31x, resp.). Furthermore, three novel implementations of the K-means clustering based on dynamic partial reconfiguration (DPR) are presented offering high degree of flexibility to dynamically reconfigure the FPGA. The DPR implementations achieved speedups in reconfiguration time between 4x to 15x.

Publisher

Hindawi Limited

Subject

Hardware and Architecture

Reference4 articles.

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. EasyNet: 100 Gbps Network for HLS;2021 31st International Conference on Field-Programmable Logic and Applications (FPL);2021-08

2. An Area-Efficient FPGA Implementation of a Real-Time Binary Object Detection System;Advances in Intelligent Systems and Computing;2020-08-20

3. BiS-KM: Enabling Any-Precision K-Means on FPGAs;Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2020-02-23

4. FPGA Dynamic and Partial Reconfiguration;ACM Computing Surveys;2019-07-31

5. Low-Complexity Scalable Architectures for Parallel Computation of Similarity Measures;Scientific Programming;2019-05-26

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