Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity

Abstract

Based on the previous achievements in improving latch-up immunity of SOI LIGBT, process simulation on our proposed VG RF SOI NLIGBT was carried out with TCAD to provide a virtually fabricated device structure. Then, an approximate latching current model was derived according to the condition of minimum regenerative feedback couple between the parasitic dual-transistors. The model indicates that its latching current is a few orders higher than those before. Further verification through device simulation was done with TCAD, which proved that its weak snapback voltage in the off state is about 0.5–2.75 times higher than those breakdown voltages reported before, its breakdown voltage in the off state is about 19 V higher than its weak snapback voltage, and its latching current density in the on state is about 2-3 orders of magnitude higher than those reported before at room temperature due to hole current bypass through P+ contact in P-well region. Therefore, it is characterized by significantly improved latch-up immunity.