Affiliation:
1. Laboratory of Electronics and Microelectronics EµE, Faculty of Sciences, Monastir University, Monastir, Tunisia
Abstract
Background:
Advances in video compression technology have been driven by everincreasing
processing power available in software and hardware.
Methods:
The emerging High-Efficiency Video Coding (HEVC) standard aims to provide a doubling in
coding efficiency with respect to the H.264/AVC high profile, delivering the same video quality at half
the bit rate.
Results:
Thus, the results show high computational complexity. In both standards, the motion
estimation block presents a significant challenge in clock latency since it consumes more than 40% of
the total encoding time. For these reasons, we proposed an optimized implementation of this algorithm
on a low-cost NVIDIA GPU developed with CUDA language.
Conclusion:
This optimized implementation can provide high-performance video encoder where the
speed reaches about 85.
Publisher
Bentham Science Publishers Ltd.
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Cited by
2 articles.
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1. An FPGA-SoC based Hardware Acceleration of Convolutional Neural Networks;2022 IEEE 9th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT);2022-05-28
2. Deep CNN Co-design for HEVC CU Partition Prediction on FPGA–SoC;Neural Processing Letters;2022-02-25