Author:
Hu Jin,Kahng Andrew B.,Kang SeokHyeong,Kim Myung-Chul,Markov Igor L.
Cited by
22 articles.
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1. A Variation-Aware Lagrangian Relaxation-Based Gate Sizing Framework for Timing Optimization;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08
2. Task-Based Parallel Programming for Gate Sizing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-04
3. DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs;ACM Transactions on Design Automation of Electronic Systems;2022-12-16
4. VirtualSync+: Timing Optimization With Virtual Synchronization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12
5. An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs;2022 IEEE 3rd International Conference on Electronics, Control, Optimization and Computer Science (ICECOCS);2022-12-01