Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing-Reference-Cited by-同舟云学术

Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing

Published:2019-05-13 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2019 on Great Lakes Symposium on VLSI
language:
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Author:

Balaji Adarsha¹,Wu Yuefeng²,Das Anup¹,Catthoor Francky³,Schaafsma Siebren²

Affiliation:

1. Drexel University, Philadelphia, PA, USA

2. Stichting IMEC Nederland, Eindhoven, Netherlands

3. IMEC Belgium & KU Leuven, Leuven, Belgium

Funder

EU-H2020

ITEA3

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3299874.3319491

Reference18 articles.

1. Filipp Akopyan et al. 2015. TrueNorth: Design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip. IEEE TCAD (2015). Filipp Akopyan et al. 2015. TrueNorth: Design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip. IEEE TCAD (2015).

2. Luca Benini and Giovanni De Micheli. 2002. Networks on chip: A new paradigm for systems on chip design. In DATE. Luca Benini and Giovanni De Micheli. 2002. Networks on chip: A new paradigm for systems on chip design. In DATE.

3. Kwabena A. Boahen. 1998. Communicating neuronal ensembles between neuromorphic chips. In Neuromorphic systems engineering. Kwabena A. Boahen. 1998. Communicating neuronal ensembles between neuromorphic chips. In Neuromorphic systems engineering.

4. J. Chen et al. 1999. Segmented bus design for low-power systems. IEEE TVLSI (1999). 10.1109/92.748197 J. Chen et al. 1999. Segmented bus design for low-power systems. IEEE TVLSI (1999). 10.1109/92.748197

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