M-CLOCK

Author:

Lee Minho1,Kang Dong Hyun1,Eom Young Ik1

Affiliation:

1. Sungkyunkwan University

Abstract

Phase Change Memory (PCM) has drawn great attention as a main memory due to its attractive characteristics such as non-volatility, byte-addressability, and in-place update. However, since the capacity of PCM is not fully mature yet, hybrid memory architecture that consists of DRAM and PCM has been suggested as a main memory. In addition, page replacement algorithm based on hybrid memory architecture is actively being studied, because existing page replacement algorithms cannot be used on hybrid memory architecture in that they do not consider the two weaknesses of PCM: high write latency and low endurance. In this article, to mitigate the above hardware limitations of PCM, we revisit the page cache layer for the hybrid memory architecture and propose a novel page replacement algorithm, called M-CLOCK, to improve the performance of hybrid memory architecture and the lifespan of PCM. In particular, M-CLOCK aims to reduce the number of PCM writes that negatively affect the performance of hybrid memory architecture . Experimental results clearly show that M-CLOCK outperforms the state-of-the-art page replacement algorithms in terms of the number of PCM writes and effective memory access time by up to 98% and 9.4 times, respectively.

Funder

Ministry of Science and ICT

Next-Generation Information Computing Development Program through the National Research Foundation of Korea

Ministry of Science, ICT

Basic Science Research Program through the National Research Foundation of Korea

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Intelligent Data Migration Policies in a Write-Optimized Copy-on-Write Tiered Storage Stack;Proceedings of the 3rd Workshop on Challenges and Opportunities of Efficient and Performant Storage Systems;2023-05-08

2. A DMA-based Swap Mechanism of Hybrid Memory System;2022 18th International Conference on Mobility, Sensing and Networking (MSN);2022-12

3. Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems;IETE Technical Review;2022-10-13

4. Online Management of Hybrid DRAM-NVMM Memory for HPC;2019 IEEE 26th International Conference on High Performance Computing, Data, and Analytics (HiPC);2019-12

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