Effective simulation and debugging for a high-level hardware language using software compilers

Author:

Pit-Claudel Clément1ORCID,Bourgeat Thomas1ORCID,Lau Stella1ORCID,Arvind 1,Chlipala Adam1

Affiliation:

1. Massachusetts Institute of Technology, USA

Funder

Defense Advanced Research Projects Agency

National Science Foundation

Sandia National Laboratories

Publisher

ACM

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Application-Level Validation of Accelerator Designs Using a Formal Software/Hardware Interface;ACM Transactions on Design Automation of Electronic Systems;2023-12-29

2. Accelerating RTL Simulation with Hardware-Software Co-Design;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

3. A Generic Framework to Develop and Verify Security Mechanisms at the Microarchitectural Level: Application to Control-Flow Integrity;2023 IEEE 36th Computer Security Foundations Symposium (CSF);2023-07

4. Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4;2023-03-25

5. RepCut: Superlinear Parallel RTL Simulation with Replication-Aided Partitioning;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3;2023-03-25

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