Compiler optimizations for eliminating barrier synchronization

Author:

Tseng Chau-Wen1

Affiliation:

1. Computer Systems Laboratory, Stanford University, Stanford, CA

Abstract

This paper presents novel compiler optimizations for reducing synchronization overhead in compiler-parallelized scientific codes. A hybrid programming model is employed to combine the flexibility of the fork-join model with the precision and power of the single-program, multiple data (SPMD) model. By exploiting compile-time computation partitions, communication analysis can eliminate barrier synchronization or replace it with less expensive forms of synchronization. We show computation partitions and data communication can be represented as systems of symbolic linear inequalities for high flexibility and precision. These optimizations has been implemented in the Stanford SUIF compiler. We extensively evaluate their performance using standard benchmark suites. Experimental results show barrier synchronization is reduced 29% on average and by several orders of magnitude for certain programs.

Publisher

Association for Computing Machinery (ACM)

Subject

Computer Graphics and Computer-Aided Design,Software

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1. Homeostasis: Design and Implementation of a Self-Stabilizing Compiler;ACM Transactions on Programming Languages and Systems;2024-05

2. High-Performance GPU-to-CPU Transpilation and Optimization via High-Level Parallel Constructs;Proceedings of the 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming;2023-02-21

3. Optimizing Barrier Synchronization on ARMv8 Many-Core Architectures;2021 IEEE International Conference on Cluster Computing (CLUSTER);2021-09

4. DisGCo;ACM Transactions on Architecture and Code Optimization;2020-12-31

5. PROBABILISTIC ANALYSIS OF LOAD-IMBALANCED PARALLEL APPLICATIONS WITH PARTIALLY ELIMINATED BARRIERS;Journal of the Operations Research Society of Japan;2015

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