Affiliation:
1. Deptartamento de Ingeniería y Tecnología de Computadores, Universidad de Murcia, Murcia, Spain
2. Departament d’Arquitectura de Computadors, Universitat Politécnica de Catalunya, Barcelona, Spain
Abstract
This article proposes a novel micro-architecture approach for mobile GPUs aimed at early removing the occluded geometry in a scene by leveraging frame-to-frame coherence, thus reducing the overall energy consumption. Mobile GPUs commonly implement a Tile-Based Rendering (TBR) architecture that differentiates two main phases: the
Geometry Pipeline
, where all the geometry of a scene is processed; and the
Raster Pipeline
, where primitives are rendered in a framebuffer. After the Geometry Pipeline, only non-culled primitives inside the camera’s frustum are stored into the
Parameter Buffer
, a data structure stored in DRAM. However, among the non-culled primitives there is a significant amount that are rendered but non-visible
at all
, resulting in useless computations. On average, 60% of those primitives are completely occluded in our benchmarks. Despite TBR architectures use on-chip caches for the Parameter Buffer, about 46% of the DRAM traffic still comes from accesses to such buffer. The proposed
Triangle Dropping
technique leverages the visibility information computed along the Raster Pipeline to predict the primitives’ visibility in the next frame to
early
discard those that will be totally occluded, drastically reducing Parameter Buffer accesses. On average, our approach achieves overall 14.5% energy savings, 28.2% energy-delay product savings, and a speedup of 20.2%.
Funder
CoCoUnit ERC Advanced Grant of the EU’s Horizon 2020
Spanish State Research Agency
ICREA Academia program
University of Murcia’s “Plan Propio de Investigación.”
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Information Systems,Software
Cited by
2 articles.
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