A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs-Reference-Cited by-同舟云学术

A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs

Published:2018-02-15 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
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Author:

Cho Shenghsun¹,Patel Mrunal¹,Chen Han¹,Ferdman Michael¹,Milder Peter¹

Affiliation:

1. Stony Brook University, Stony Brook, NY, USA

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3174243.3174269

Reference24 articles.

1. Altera. 2017. Quartus Prime Standard Edition Handbook. Altera. 2017. Quartus Prime Standard Edition Handbook.

2. Amazon 2017. Amazon EC2 F1 FPGA Instances. (2017). https://aws.amazon.com/ ec2/instance-types/f1 Amazon 2017. Amazon EC2 F1 FPGA Instances. (2017). https://aws.amazon.com/ ec2/instance-types/f1

3. Amazon 2017. Amazon EC2 F1 FPGA Simulation Environment. (2017). https://github.com/aws/aws-fpga/blob/master/hdk/docs/RTL_Simulating_CL_ Designs.md Amazon 2017. Amazon EC2 F1 FPGA Simulation Environment. (2017). https://github.com/aws/aws-fpga/blob/master/hdk/docs/RTL_Simulating_CL_ Designs.md

4. Intel 2015. Intel OpenCL for FPGA. (2015). https://www.altera.com/products/ design-software/embedded-software-developers/opencl/overview.html Intel 2015. Intel OpenCL for FPGA. (2015). https://www.altera.com/products/ design-software/embedded-software-developers/opencl/overview.html

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