Defect-Tolerant Mapping of CMOL Circuits with Delay Optimization
Author:
Affiliation:
1. Ningbo University, Ningbo, China
Funder
National Natural Science Foundation of China
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3386263.3406944
Reference14 articles.
1. CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices
2. Hybrid CMOS/Nanoelectronic Circuits: Opportunities and Challenges
3. Katsuhiko Ariga Michael V. Lee Taizo Mori Xiao-Yan Yu and Jonathan P. Hill. Two-dimensional nanoarchitectonics based on self-assembly. Advances in Colloid & Interface Science 154(1--2):20--29 2010. Katsuhiko Ariga Michael V. Lee Taizo Mori Xiao-Yan Yu and Jonathan P. Hill. Two-dimensional nanoarchitectonics based on self-assembly. Advances in Colloid & Interface Science 154(1--2):20--29 2010.
4. Nanoelectronics from the bottom up
5. High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing
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2. Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization;Journal of Computer Science and Technology;2021-09-30
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