Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization-Reference-Cited by-同舟云学术

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Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization

Published:2021-09-30 Issue:5 Volume:36 Page:1118-1132
ISSN:1000-9000
Container-title:Journal of Computer Science and Technology
language:en
Short-container-title:J. Comput. Sci. Technol.

Author:

Zha Xiao-Jing,Xia Yin-Shui,Xie Shang-Luan,Chu Zhu-Fei

Publisher

Springer Science and Business Media LLC

Subject

Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software

Link

https://link.springer.com/content/pdf/10.1007/s11390-021-0904-0.pdf

Reference26 articles.

1. Goldstein S C, Budiu M. Nanofabrics: Spatial computing using molecular electronics. SIGARCH Comput. Archit. News, 2001, 29(2): 178-191. https://doi.org/10.1145/384285.379262.

2. DeHon A. Nanowire-based programmable architectures. J. Emerg. Technol. Comput. Syst., 2005, 1(2): 109-162. https://doi.org/10.1145/1084748.1084750.

3. Lu W, Lieber C M. Nanoelectronics from the bottom up. Nature Materials, 2007, 6(11):841-850. https://doi.org/10.1038/nmat2028.

4. Strukov D B, Likharev K K. CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices. Nanotechnology, 2005, 16(6): 888-900. https://doi.org/10.1088/0957-4484/16/6/045.

5. Likharev K K. Hybrid CMOS/nanoelectronic circuits: Opportunities and challenges. J. Nanoelectron. Optoelectron., 2008, 3(3): 203-230. https://doi.org/10.1166/jno.2008.301.

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