Reliability-Enhanced Circuit Design Flow Based on Approximate Logic Synthesis
Author:
Affiliation:
1. Peking University, BeiJing, China
2. Shanghai Jiao Tong University, Shanghai, China
3. Cornell University, Ithaca, NY, USA
Funder
the National Key R&D Program of China
NSFC
111 Project
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3386263.3406926
Reference23 articles.
1. Design for reliability with the advanced integrated circuit (IC) technology: challenges and opportunities
2. Cross-Layer Modeling and Simulation of Circuit Reliability
3. System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection
4. A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging
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