Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement-Reference-Cited by-同舟云学术

Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement

Published:2019-04-04 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2019 International Symposium on Physical Design
language:
Short-container-title:

Author:

Chang Hua-Yu¹,Jiang Iris Hui-Ru²

Affiliation:

1. Synopsys, Inc., Taipei, Taiwan Roc

2. National Taiwan University, Taipei, Taiwan Roc

Funder

Ministry of Science and Technology, Taiwan

Synopsys

Taiwan Semiconductor Manufacturing Company

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3299902.3309755

Reference19 articles.

1. D. Abercrombie. 2017. Will EUV kill multi-patterning? (January 2017). Semiconductor Engineering. Retrieved from https://semiengineering.com/will-euv-kill-multi-patterning/ D. Abercrombie. 2017. Will EUV kill multi-patterning? (January 2017). Semiconductor Engineering. Retrieved from https://semiengineering.com/will-euv-kill-multi-patterning/

2. ITRS lithography roadmap: 2015 challenges;Neisser M.;Adv. Opt. Techn.,2015

3. M. van den Brink. 2014. Many ways to shrink: the right moves to 10 nanometer and beyond. (November 2014). Retrieved from https://staticwww.asml.com/doclib/investor/asml_3_Investor_Day-Many_ways_to_shrink_MvdBrink1.pdf M. van den Brink. 2014. Many ways to shrink: the right moves to 10 nanometer and beyond. (November 2014). Retrieved from https://staticwww.asml.com/doclib/investor/asml_3_Investor_Day-Many_ways_to_shrink_MvdBrink1.pdf

4. Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography

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