1. Chang H-Y, Jiang IH-R (2019) Multiple patterning layout compliance with minimizing topology disturbance and polygon displacement. In: Proceedings of the 2019 international symposium on physical design. ISPD ’19. Association for Computing Machinery, New York, NY, USA, pp 93–100
2. Chang Y-W, Liu R-G, Fang S-Y (2015) Euv and e-beam manufacturability: challenges and solutions. In: Proceedings of the 52nd annual design automation conference (DAC), ACM, pp 198–203
3. Chase JG, Smith BW (2001) Overview of modern lithography techniques and a mems-based approach to high throughput rate electron beam lithography. J Intell Mater Syst Struct 12(12):807–817
4. Ding Y, Chu C, Mak W-K (2014) Throughput optimization for sadp and e-beam based manufacturing of 1d layout. In: Proceedings of the 51st annual design automation conference (DAC), ACM, pp 1–6
5. Du Y, Zhang H, Wong MD, Chao K-Y (2012) Hybrid lithography optimization with e-beam and immersion processes for 16nm 1d gridded design. In: Proceedings of 17th Asia and South Pacific design automation conference (ASP-DAC), IEEE, pp 707–712