Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex Caching-Reference-Cited by-同舟云学术

Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex Caching

Published:2019-02-20 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
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Author:

Shao Zhiyuan¹,Li Ruoshi¹,Hu Diqing¹,Liao Xiaofei¹,Jin Hai¹

Affiliation:

1. Huazhong University of Science and Technology, Wuhan, China

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3289602.3293900

Reference26 articles.

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3. Scott Beamer Krste Asanovic and David Patterson. 2015. Locality Exists in Graph Processing: Workload Characterization on an Ivy Bridge Server. In IISWC. IEEE 56--65. 10.1109/IISWC.2015.12 Scott Beamer Krste Asanovic and David Patterson. 2015. Locality Exists in Graph Processing: Workload Characterization on an Ivy Bridge Server. In IISWC. IEEE 56--65. 10.1109/IISWC.2015.12

4. FPGP

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