The challenge of multi-operand adders in CNNs on FPGAs

Author:

Abdelouahab Kamel1,Pelcat Maxime2,Berry Francois1

Affiliation:

1. Universite Clermont Auvergne, Clermont Ferrand, France

2. Institut Pascal, INSA Rennes, Rennes, France

Funder

Labex

Ministère de l'Education Nationale, de l'Enseignement Superieur et de la Recherche

Publisher

ACM

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Vedic Multiplier and Wallace Tree Adders Based Optimised Processing Element Unit for CNN on FPGA;2022 IEEE International Power and Renewable Energy Conference (IPRECON);2022-12-16

2. Energy-Efficient Approximate Booth Multipliers for Convolutional Neural Networks;2022 19th International Bhurban Conference on Applied Sciences and Technology (IBCAST);2022-08-16

3. Bit-Serial multiplier based Neural Processing Element with Approximate adder tree;2020 International SoC Design Conference (ISOCC);2020-10-21

4. On building a CNN-based multi-view smart camera for real-time object detection;Microprocessors and Microsystems;2020-09

5. A novel cognitive Wallace compressor based multi operand adders in CNN architecture for FPGA;Journal of Ambient Intelligence and Humanized Computing;2020-08-07

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