gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator-Reference-Cited by-同舟云学术

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator

Published:2021-08-09 Issue: Volume: Page:
ISSN:
Container-title:50th International Conference on Parallel Processing
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Author:

López-Paradís Guillem¹,Armejach Adrià¹,Moretó Miquel¹

Affiliation:

1. BARCELONA SUPERCOMPUTING CENTER, Spain

Funder

ERDF Operational Program of Catalonia 2014-2020

Ministerio de Ciencia, Innovación y Universidades

Horizon 2020 Framework Programme

Juan de la Cierva postdoctoral fellowship

Ajuts per a la contractació de personal investigador novell

Ramón y Cajal fellowship

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3472456.3472461

Reference37 articles.

1. 2018. NVDLA Github webpage. (2018). https://github.com/nvdla/hw 2018. NVDLA Github webpage. (2018). https://github.com/nvdla/hw

2. Anandtech. 2019. Hot Chips 31: Tesla Solution for Full Self Driving Car. (2019). https://www.anandtech.com/show/14766/hot-chips-31-live-blogs-tesla-solution-for-full-self-driving Anandtech. 2019. Hot Chips 31: Tesla Solution for Full Self Driving Car. (2019). https://www.anandtech.com/show/14766/hot-chips-31-live-blogs-tesla-solution-for-full-self-driving

3. COTSon

4. ARM. 2011. AMBA AXI and ACE Protocol Specification.(2011). https://static.docs.arm.com/ihi0022/g/IHI0022G_amba_axi_protocol_spec.pdf ARM. 2011. AMBA AXI and ACE Protocol Specification.(2011). https://static.docs.arm.com/ihi0022/g/IHI0022G_amba_axi_protocol_spec.pdf

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