A New Implementation of 16-bit Parallel Prefix Adder for High Speed and Low Area

Author:

Liao Qing1,Li Shuguo1

Affiliation:

1. Department of Microelectronics and Nanoelectronics, Tsinghua University, Beijing, China

Publisher

ACM

Reference10 articles.

1. Synthesis of adaptable hybrid adders for area optimization under timing constraint;Yonghwan K.;ACM Transactions on Design Automation of Electronic Systems.,2012

2. Parallel Prefix Computation

3. Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2;Yen;ACM Transactions on Design Automation of Electronic Systems. 15,2009

4. On the construction of zero-deficiency parallel prefix circuits with minimum depth;Haikun Z.;ACM Transactions on Design Automation of Electronic Systems.,2006

5. A parallel algorithm for the efficient solution of a general class of recurrence equations;Kogge P. M.;IEEE Trans. Computers.,1973

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder;ACM Transactions on Design Automation of Electronic Systems;2024-04-22

2. Design and implementation of DA-RFIR filter for effective removal of noise from audio signal for SDR applications;SEVENTH INTERNATIONAL SYMPOSIUM ON NEGATIVE IONS, BEAMS AND SOURCES (NIBS 2020);2021

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