HAP

Author:

Wei Wei1,Jiang Dejun1,Xiong Jin1,Chen Mingyu1

Affiliation:

1. State Key Laboratory of Computer Architecture Institute of Computing Technology, Chinese Academy of Sciences; University of Chinese Academy of Sciences, Beijing China

Abstract

Data-center servers benefit from large-capacity memory systems to run multiple processes simultaneously. Hybrid DRAM-NVM memory is attractive for increasing memory capacity by exploiting the scalability of Non-Volatile Memory (NVM). However, current LLC policies are unaware of hybrid memory. Cache misses to NVM introduce high cost due to long NVM latency. Moreover, evicting dirty NVM data suffer from long write latency. We propose hybrid memory aware cache partitioning to dynamically adjust cache spaces and give NVM dirty data more chances to reside in LLC. Experimental results show Hybrid-memory-Aware Partition (HAP) improves performance by 46.7% and reduces energy consumption by 21.9% on average against LRU management. Moreover, HAP averagely improves performance by 9.3% and reduces energy consumption by 6.4% against a state-of-the-art cache mechanism.

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Information Systems,Software

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems;IETE Technical Review;2022-10-13

2. Management of Cloud Data in Heterogeneously Integrated Main Memory;2021 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia);2021-11-01

3. NVLSM: A Persistent Memory Key-Value Store Using Log-Structured Merge Tree with Accumulative Compaction;ACM Transactions on Storage;2021-08-31

4. Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System;ACM Transactions on Design Automation of Electronic Systems;2020-05-14

5. Reducing Writebacks Through In-Cache Displacement;ACM Transactions on Design Automation of Electronic Systems;2019-03-21

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