SPIRE-Reference-Cited by-同舟云学术

SPIRE

Published:1992-03 Issue:1 Volume:20 Page:45-54
ISSN:0163-5964
Container-title:ACM SIGARCH Computer Architecture News
language:en
Short-container-title:SIGARCH Comput. Archit. News

Author:

Wajda Eligiusz

Abstract

The SPIRE-Architecture is designed for high speed uniprocessor execution of sequential problems as well for parallel multiprocessor systems where individual processors perform operations on complex data structures. The idea of SPIRE-Architecture lies in a new instruction format expanded by a dedicated execution clause and compilative instruction execution. To mirror this concept in practice some new components has been added to the hardware.The simulation results show that SPIRE can processes data up to 30 times faster than classic von Neumann processor and profits directly from complexity of used data structures. Programm code is about twice as compact as that of RISC processors. Furthermore, a proposed hardware concept and consistent rules of instruction coding allows compilers to generate very efficient code.

Publisher

Association for Computing Machinery (ACM)

Link

https://dl.acm.org/doi/pdf/10.1145/130823.130825

Reference30 articles.

1. 1 . "The Cray-1 Computer System" R.M. Russel CACM Jan. 1987 Vol. 21 No. 1. 10.1145/359327.359336 1. "The Cray-1 Computer System" R.M. Russel CACM Jan. 1987 Vol. 21 No. 1. 10.1145/359327.359336

2. A vector and array multiprocessor extension of the sylvan architecture

3. 3 . David A. Patterson "Reduced Instruction Set Computers" CACM January 1985 Vol. 28 Number 1. 10.1145/2465.214917 3. David A. Patterson "Reduced Instruction Set Computers" CACM January 1985 Vol. 28 Number 1. 10.1145/2465.214917

4. 4 . "iAPX 432 User's Manual" INTEL May 1983. 4. "iAPX 432 User's Manual" INTEL May 1983.