Affiliation:
1. Univ. of Technology, Delft, The Netherlands
Abstract
This paper presents an overview of deterministic functional RAM chip testing. Instead of the traditional ad-hoc approach toward developing memory test algorithms, a hierarchy of functional faults and tests is presented, which is shown to cover all likely functional memory faults. This is done by presenting a novel way of categorizing the faults. All (possible) fault combinations are discussed. Requirements are put forward under which conditions a fault combination can be detected. Finally, memory test algorithms that satisfy the given requirements are presented.
Publisher
Association for Computing Machinery (ACM)
Subject
General Computer Science,Theoretical Computer Science
Cited by
37 articles.
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