Efficient Address Translation for Architectures with Multiple Page Sizes-Reference-Cited by-同舟云学术

Efficient Address Translation for Architectures with Multiple Page Sizes

Published:2017-04-04 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems
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Author:

Cox Guilherme¹,Bhattacharjee Abhishek¹

Affiliation:

1. Rutgers University, Piscataway, NJ, USA

Funder

Google

VMWare

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3037697.3037704

Reference49 articles.

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2. Surpassing the TLB performance of superpages with less operating system support

3. M. Talluri S. Kong M. Hill and D. Patterson "Tradeoffs in Supporting Two Page Sizes " ISCA 1992. M. Talluri S. Kong M. Hill and D. Patterson "Tradeoffs in Supporting Two Page Sizes " ISCA 1992.

4. B. Pham J. Vesely G. Loh and A. Bhattacharjee "Large P ages and Lightweight Memory Management in Virtualized Systems: Can You Have it Both Ways? " MICRO 2015. B. Pham J. Vesely G. Loh and A. Bhattacharjee "Large P ages and Lightweight Memory Management in Virtualized Systems: Can You Have it Both Ways? " MICRO 2015.

5. An energy efficient TLB design methodology

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