Author:
Chang Chia-Ming,Huang Shih-Hsu,Ho Yuan-Kai,Lin Jia-Zong,Wang Hsin-Po,Lu Yu-Sheng
Cited by
9 articles.
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1. Frequency Scaling for High Performance of Low-End Pipelined Processors;Advances in Science, Technology and Engineering Systems Journal;2021-03
2. Low Voltage Clock Tree Synthesis with Local Gate Clusters;Proceedings of the 2019 on Great Lakes Symposium on VLSI;2019-05-13
3. Clock Design and Synthesis;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
4. Power-mode-aware buffer synthesis for low-power clock skew minimization;IEICE Electronics Express;2016
5. Clock gating methodologies and tools: a survey;International Journal of Circuit Theory and Applications;2015-06-15