Power-mode-aware buffer synthesis for low-power clock skew minimization-Reference-Cited by-同舟云学术

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Power-mode-aware buffer synthesis for low-power clock skew minimization

Published:2016 Issue:14 Volume:13 Page:20160511-20160511
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Huang Shih-Hsu¹,Cheng Chun-Hua¹

Affiliation:

1. Department of Electronic Engineering, Chung Yuan Christian University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/13/14/13_13.20160511/_pdf

Reference11 articles.

1. [1] T. Simunic, et al.: “Dynamic voltage scaling and power management for portable systems,” Proc. of IEEE Design Automation Conference (2001) 524 (DOI: 10.1109/DAC.2001.156195).

2. [2] B. Brock and K. Rajamani: “Dynamic power management for embedded systems,” Proc. of IEEE International SOC Conference (2003) 416 (DOI: 10.1109/SOC.2003.1241556).

3. [3] A. C. Orgerieet al.: “A survey on techniques for improving the energy efficiency of large-scale distributed systems,” ACM Comput. Surv. 46 (2014) 47 (DOI: 10.1145/2532637).

4. [4] A. D. Mehta, et al.: “Clustering and load balancing for buffered clock tree synthesis,” Proc. of IEEE International Conference on Computer Design (1997) 217 (DOI: 10.1109/ICCD.1997.628871).

5. [5] K. K. Ryooet al.: “A new clock routing algorithm using link-edge insertion for high performance IC design,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E83-A [6] (2000).

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