A refinement calculus for the synthesis of verified hardware descriptions in VHDL

Author:

Breuer Peter T.1,Delgado Carlos Kloos1,Marín Andrés López1,Martínez Madrid Natividad1,Sánchez Fernández Luis2

Affiliation:

1. Area de Ingeniería Telemática, Departmento Ingeniería, Universidad Carlos III de Madrid, Butarque 15, E-28911 Leganés, Madrid, Spain

2. Departmento Ingeniería de Sistemas Telemáticos, ETSI Telecomunicación, Universidad Politécnica de Madrid, Ciudad Universitaria, E-28040 Madrid, Spain

Abstract

A formal refinement calculus targeted at system-level descriptions in the IEEE standard hardware description language VHDL is described here. Refinement can be used to develop hardware description code that is “correct by construction”. the calculus is closely related to a Hoare-style programming logic for VHDL and real-time systems in general. That logic and a semantics for a core subset of VHDL are described. The programming logic and the associated refinement calculus are shown to be complete. This means that if there is a code that can be shown to implement a given specification, then it will be derivable from the specification via the calculus.

Publisher

Association for Computing Machinery (ACM)

Subject

Software

Reference31 articles.

1. Stepwise refinement of action systems;BACK R.-J.;Struct. Program.,1991

2. Denotational semantics of a synchronous VHDL subset

3. Formal verification of VHDL descriptions in the Prevail environment

4. Lecture Notes in Computer Science;BOSE B.

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