Performance Impact of a Slower Main Memory
Author:
Affiliation:
1. Barcelona Supercomputing Center (BSC), Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
2. BSC & UPC, Barcelona, Spain
3. Memory Planning Group, Samsung Electronics Co., Ltd, Seoul, Korea
4. BSC, Barcelona, Spain
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2989081.2989082
Reference54 articles.
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2. Avinash Sodani. Race to Exascale: Opportunities and Challenges. Keynote Presentation at the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 2011. Avinash Sodani. Race to Exascale: Opportunities and Challenges. Keynote Presentation at the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 2011.
3. Rick Stevens Andy White Pete Beckman Ray Bair-ANL Jim Hack Jeff Nichols Al GeistORNL Horst Simon Kathy Yelick John Shalf-LBNL Steve Ashby Moe Khaleel-PNNL Michel McCoy Mark Seager Brent Gorda-LLNL John Morrison Cheryl Wampler-LANL James Peery Sudip Dosanjh Jim Ang-SNL Jim Davenport Tom Schlagel BNL Fred Johnson and Paul Messina. A Decadal DOE Plan for Providing Exascale Applications and Technologies for DOE Mission Needs. Presentation at Advanced Simulation and Computing Principal Investigators Meeting March 2010. Rick Stevens Andy White Pete Beckman Ray Bair-ANL Jim Hack Jeff Nichols Al GeistORNL Horst Simon Kathy Yelick John Shalf-LBNL Steve Ashby Moe Khaleel-PNNL Michel McCoy Mark Seager Brent Gorda-LLNL John Morrison Cheryl Wampler-LANL James Peery Sudip Dosanjh Jim Ang-SNL Jim Davenport Tom Schlagel BNL Fred Johnson and Paul Messina. A Decadal DOE Plan for Providing Exascale Applications and Technologies for DOE Mission Needs. Presentation at Advanced Simulation and Computing Principal Investigators Meeting March 2010.
4. Hitting the memory wall
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