Affiliation:
1. Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA Laboratory, Grenoble Cedex, France
Abstract
During the formal functional verification of Register-Transfer Level designs, a false failure is often observed. Most of the time, this failure is caused by an underconstrained model. The analysis of the root cause for the verification error and the creation of missing assumptions are a significant time burden. In this article, we present a methodology to automatically mine these missing assumptions from counter-examples. First, multiple counter-examples are generated for the same property. Then, relevant behaviors are mined from the counter-examples. Finally, corresponding assumptions are filtered and a small amount is returned to the user for review.
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Software