Physical Design at the Transistor Level Beyond Standard-Cell Methodology
Author:
Affiliation:
1. Synopsys Inc., Hillsboro, OR, USA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3505170.3511476
Reference16 articles.
1. Standard cell routing via boolean satisfiability
2. Area-Optimal Transistor Folding for 1-D Gridded Cell Design
3. Automatic Cell Layout in the 7nm Era
4. A. Sorokin and N. Ryzhenko . Sat-based placement adjustment of finfets inside unroutable standard cells targetting feasible drc-clean routing . In GLSVLSI , 2019 . A. Sorokin and N. Ryzhenko. Sat-based placement adjustment of finfets inside unroutable standard cells targetting feasible drc-clean routing. In GLSVLSI, 2019.
5. Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation
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1. TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
2. CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01
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