Affiliation:
1. Hewlett-Packard Laboratories
2. Hewlett-Packard Laboratiorie
Abstract
As part of an effort to develop an optimizing compiler for a pipelined architecture, a code reorganization algorithm has been developed that significantly reduces the number of runtime pipeline interlocks. In a pass after code generation, the algorithm uses a dag representation to heuristically schedule the instructions in each basic block.
Previous algorithms for reducing pipeline interlocks have had worst-case runtimes of at least
O
(
n
4
). By using a dag representation which prevents scheduling deadlocks and a selection method that requires no lookahead, the resulting algorithm reorganizes instructions almost as effectively in practice, while having an
O
(
n
2
) worst-case runtime.
Publisher
Association for Computing Machinery (ACM)
Subject
Computer Graphics and Computer-Aided Design,Software
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