Affiliation:
1. University of Michigan, Ann Arbor
Abstract
VLSI placement optimizes locations of circuit components so as to reduce interconnect. Formulated in terms of (hyper) graphs, it is NP-hard, and yet must be solved for challenging million-node instances within several hours. We propose an algorithm for large-scale placement that outperforms prior art both in runtime and solution quality on standard benchmarks. The algorithm is more straightforward than existing placers and easier to integrate into timing-closure flows. Our C++ implementation is compact, self-contained and exploits instruction-level and thread-level parallelism. Due to its simplicity and superior performance, the algorithm has been adopted in the industry and was extended by several university groups to multi-objective optimization.
Funder
Intel Corporation
International Business Machines Corporation
Publisher
Association for Computing Machinery (ACM)
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. An Adaptive Analytical FPGA Placement flow based on Reinforcement Learning;2023 International Conference on Microelectronics (ICM);2023-12-17
2. FPGA Placement: Dynamic Decision Making Via Machine Learning;2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2023-08-28
3. An Adaptive Sequential Decision Making Flow for FPGAs using Machine Learning;2022 International Conference on Microelectronics (ICM);2022-12-04
4. Exploiting Net Connectivity in Legalization and Detailed Placement Scenarios;Information;2022-04-20
5. Closing the Gap between Global and Detailed Placement;Proceedings of the 2015 Symposium on International Symposium on Physical Design;2015-03-29