Differentiable-timing-driven global placement

Author:

Guo Zizheng1,Lin Yibo1

Affiliation:

1. Peking University

Funder

National Key Research and Development Program of China

National Science Foundation of China

111 Project

Publisher

ACM

Reference35 articles.

1. Architecture and details of a high quality, large-scale analytical placer;Kahng A. B.;Proc. ICCAD. IEEE,2005

2. Multilevel generalized force-directed method for circuit placement;Chan T.;Proc. ISPD. ACM,2005

3. A faster implementation of APlace;Kahng A. B.;Proc. ISPD. ACM,2006

4. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints

5. NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs

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3. Implementation of a PnR Flow at Block Level to Achieve the High Utilisation Rate;2024 International Conference on Inventive Computation Technologies (ICICT);2024-04-24

4. Electrostatics-Based Analytical Global Placement for Timing Optimization;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

5. Timing-Driven Analytical Placement According to Expected Cell Distribution Range;Proceedings of the 2024 International Symposium on Physical Design;2024-03-12

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