The BRISC-V Platform

Author:

Agrawal Rashmi1,Bandara Sahan1,Ehret Alan1,Isakov Mihailo1,Mark Miguel1,Kinsy Michel A.1

Affiliation:

1. Adaptive and Secure Computing Systems (ASCS) Laboratory, Boston University, Boston, Massachusetts

Publisher

ACM Press

Reference5 articles.

1. Sahan Bandara, Alan Ehret, Donato Kava, and Michel Kinsy. 2019. BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox. In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '19). ACM, New York, NY, USA, 306--306. https://doi.org/10.1145/3289602.3293991

2. N. Boskov, M Isakov, and M. A. Kinsy. 2019. CodeTrolley: Hardware-Assisted Control Flow Obfuscation. Boston Area Architecture 2019 Workshop (BARC19) (Jan. 2019). arXiv:1903.00841

3. Michael Graziano, Miguel Mark, Stefan Gvozdenovic, and Michel A. Kinsy. 2019. Hardware Assisted Transparent ROP Mitigation for RISC-V. Boston Area Architecture 2019 Workshop (BARC19) (Jan. 2019).

4. Chi-Keung Luk, Robert Cohn, Robert Muth, Harish Patil, Artur Klauser, Geoff Lowney, Steven Wallace, Vijay Janapa Reddi, and Kim Hazelwood. 2005. Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation. In Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '05). ACM, New York, NY, USA, 190--200. https://doi.org/10.1145/1065010.1065034

5. A Waterman and K Asanovic. 2017. The RISC-V Instruction Set Manual-Volume I: User-Level ISA-Document Version 2.2. RISC-V Foundation (May 2017) (2017).

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