A Practical Computer Architecture Education with RISC-V and TL-Verilog-Reference-Cited by-同舟云学术

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A Practical Computer Architecture Education with RISC-V and TL-Verilog

Published:2023-09-13 Issue: Volume: Page:
ISSN:
Container-title:2023 XXXII International Scientific Conference Electronics (ET)
language:
Short-container-title:

Author:

Minev Petar¹,Kukenska Valentina¹,Varbov Ilian¹,Dinev Matyo¹

Affiliation:

1. Technical University of Gabrovo,Faculty of Electrical Engineering and Electronics,Department of Computer Systems and Technologies,Gabrovo,Bulgaria,5300

Funder

Ministry of Education

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10278503/10278560/10279744.pdf?arnumber=10279744

Reference17 articles.

1. Verilator and SystemPerl;snyder;North American SystemC Users' Group Design Automation Conference,0

2. RISC-V ABIs Specification, Document Version 1.0;cheng;RISC-V International,2022

3. Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering;impagliazzo;Technical Report,2016

4. An Integrated Learning Approach Used in Computer Architecture

5. Top-Down Transaction-Level Design with TL-Verilog;hoover;CoRR,2018

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