Hardware Specialization: Estimating Monte Carlo Cross-Section Lookup Kernel Performance and Area

Author:

Yoshii Kazutomo1ORCID,Tramm John2ORCID,Allen Bryce1ORCID,Ueno Tomohiro3ORCID,Sano Kentaro3ORCID,Siegel Andrew1ORCID,Beckman Pete2ORCID

Affiliation:

1. Argonne National Laboratory, USA

2. Argonne National Laboratory, United States of America

3. RIKEN Center for Computational Science (R-CCS), Japan

Publisher

ACM

Reference15 articles.

1. LogCA: A Performance Model for Hardware Accelerators

2. J Bachrach , H Vo , B Richards , and Y Lee DAC an d 2012 Design. 2012. Chisel: constructing hardware in a Scala embedded language . DAC Design Automation Conference ( 2012 ), 1212–1221. J Bachrach, H Vo, B Richards, and Y Lee DAC an d 2012 Design. 2012. Chisel: constructing hardware in a Scala embedded language. DAC Design Automation Conference (2012), 1212–1221.

3. JW Jonathan Bachrach and Krste Asanović. 2017. Chisel 3.0 Tutorial. EECS Department UC Berkeley Tech. Rep. (2017). JW Jonathan Bachrach and Krste Asanović. 2017. Chisel 3.0 Tutorial. EECS Department UC Berkeley Tech. Rep. (2017).

4. Chiplet actuary

5. 5.6 Mb/mm $^{2}$ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology

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