Author:
Lee Hsien-Hsin S.,Tyson Gary S.,Farrens Matthew K.
Cited by
32 articles.
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1. DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04
2. IR-ORAM: Path Access Type Based Memory Intensity Reduction for Path-ORAM;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04
3. Writeback-Aware LLC Management for PCM-Based Main Memory Systems;ACM Transactions on Design Automation of Electronic Systems;2019-03-21
4. Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems;ACM Transactions on Design Automation of Electronic Systems;2019-01-11
5. Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication;2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO);2018-10