Affiliation:
1. Shenzhen University, Shenzhen, China
Abstract
Three-dimensional (3D) flash memory is an emerging memory technology that enables a number of improvements to conventional planar NAND flash memory, including larger capacity, less program disturbance, and lower access latency. In contrast to conventional planar flash memory, 3D flash memory adopts charge-trapping mechanism. NAND strings punch through multiple stacked layers to form the three-dimensional infrastructure. However, the etching processes for NAND strings are unable to produce perfectly vertical features, especially on the scale of 20 nanometers or less. The process variation will cause uneven distribution of electrons, which poses a threat to the integrity of data stored in flash.
This paper present
P-Alloc
, a process-variation tolerant reliability management strategy for 3D charge-trapping flash memory. P-Alloc offers both hardware and software support to allocate data to the 3D flash in the presence of process variation. P-Alloc predicts the state of a physical page, i.e., the basic unit for each write or read operation in flash memory, and tries to assign critical data to more reliable pages. A hardware-based voltage threshold compensation scheme is also proposed to further reduce the faults. We demonstrate the viability of the proposed scheme using a variety of realistic workloads. Our extensive evaluations show that, P-Alloc significantly enhances the reliability and reduces the access latency compared to the baseline scheme.
Funder
Shenzhen Science and Technology Foundation
Natural Science Foundation of SZU
State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
National Natural Science Foundation of China
China 863
Guangdong Natural Science Foundation
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Software
Cited by
17 articles.
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