A Performance Model to Execute Workflows on High-Bandwidth-Memory Architectures-Reference-Cited by-同舟云学术

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A Performance Model to Execute Workflows on High-Bandwidth-Memory Architectures

Published:2018-08-13 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 47th International Conference on Parallel Processing
language:
Short-container-title:

Author:

Benoit Anne¹,Perarnau Swann²,Pottier Loïc³,Robert Yves⁴

Affiliation:

1. École Normale Supérieure de Lyon, Lyon, France and Georgia Institute of Technology, Atlanta, GA

2. Argonne National Laboratory, Argonne, Illinois, USA

3. École Normale Supérieure de Lyon, Lyon, France

4. École Normale Supérieure de Lyon, Lyon, France and University of Tennessee, Knoxville, TN

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3225058.3225110

Reference22 articles.

1. Data-Aware Task Scheduling on Multi-accelerator Based Platforms

2. StarPU: a unified platform for task scheduling on heterogeneous multicore architectures

3. Anne Benoit Swann Perarnau Loïc Pottier and Yves Robert. 2018. A performance model to execute workflows on high-bandwidth memory architectures. Research report RR-9165. INRIA. Available at hal.inria.fr. Anne Benoit Swann Perarnau Loïc Pottier and Yves Robert. 2018. A performance model to execute workflows on high-bandwidth memory architectures. Research report RR-9165. INRIA. Available at hal.inria.fr.

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Rapid Execution Time Estimation for Heterogeneous Memory Systems Through Differential Tracing;Lecture Notes in Computer Science;2022

2. Modeling the Performance of Scientific Workflow Executions on HPC Platforms with Burst Buffers;2020 IEEE International Conference on Cluster Computing (CLUSTER);2020-09

3. Pattern-Aware Staging for Hybrid Memory Systems;Lecture Notes in Computer Science;2020

4. Explicit Data Layout Management for Autotuning Exploration on Complex Memory Topologies;2019 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC);2019-11

5. A Performance Model to Execute Workflows on High-Bandwidth-Memory Architectures;Proceedings of the 47th International Conference on Parallel Processing;2018-08-13

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