Bus-Contention Aware Schedulability Analysis for the 3-Phase Task Model with Partitioned Scheduling
Author:
Affiliation:
1. CISTER Research Centre and ISEP, Polytechnic Institute of Porto, Portugal
2. Eindhoven University of Technology (TU/e) Eindhoven, Netherlands
Funder
FCT/MCTES (Portuguese Foundation for Science and Technology)
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3453417.3453433
Reference26 articles.
1. Schedulability analysis of global memory-predictable scheduling
2. Worst-Case Response Time Analysis of Real-Time Tasks under Fixed-Priority Scheduling with Deferred Preemption Revisited
3. A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling
4. Modeling shared cache and bus in multi-cores for timing analysis
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3. Contention-free scheduling of PREM tasks on partitioned multicore platforms;2022 IEEE 27th International Conference on Emerging Technologies and Factory Automation (ETFA);2022-09-06
4. Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration scheme;Journal of Systems Architecture;2022-01
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