Modeling shared cache and bus in multi-cores for timing analysis-Reference-Cited by-同舟云学术

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Modeling shared cache and bus in multi-cores for timing analysis

Published:2010 Issue: Volume: Page:
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Container-title:Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems - SCOPES '10
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Author:

Chattopadhyay Sudipta,Roychoudhury Abhik,Mitra Tulika

Publisher

ACM Press

Cited by 25 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Assessing Intel’s Memory Bandwidth Allocation for resource limitation in real-time systems;2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC);2022-05-17

2. Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration scheme;Journal of Systems Architecture;2022-01

3. Bus-Contention Aware Schedulability Analysis for the 3-Phase Task Model with Partitioned Scheduling;29th International Conference on Real-Time Networks and Systems;2021-04-07

4. Cache-conscious off-line real-time scheduling for multi-core platforms: algorithms and implementation;Real-Time Systems;2019-03-06

5. An extensible framework for multicore response time analysis;Real-Time Systems;2017-07-18

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