Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs
Author:
Affiliation:
1. Georgia Institute of Technology
2. Technology Research, GLOBALFOUNDRIES
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2966986.2967080
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5. Design and CAD methodologies for low power gate-level monolithic 3D ICs
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